1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to an array substrate for a fringe field switching mode liquid crystal display and a method of manufacturing the same.
2. Discussion of the Related Art
Until recently, display devices have typically used cathode-ray tubes (CRTs). Presently, many efforts and studies are being made to develop various types of flat panel displays, such as liquid crystal displays (LCD), plasma display panels (PDPs), field emission displays, and electro-luminescence displays (ELDs), as a substitute for CRTs. Of these flat panel displays, LCD have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD includes two substrates that are spaced apart and face each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes that face each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes in accordance with the intensity of the induced electric field into the direction of the induced electric field, thereby changing the light transmissivity of the LCD. Thus, the LCD displays images by varying the intensity of the induced electric field.
However, the LCD operated by the electric field induced between the two electrodes on the two substrates does not have wide viewing angle property. To solve this problem, an in-plane switching (IPS) mode LCD is suggested.
FIG. 1 is a schematic cross-sectional view illustrating an IPS mode LCD.
Referring to FIG. 1, the IPS mode LCD includes a lower substrate 10 as an array substrate, an upper substrate 9 as a color filter substrate, and a liquid crystal layer 11 between the two substrates 9 and 10.
A common electrode 17 and a pixel electrode 30 is formed at the lower substrate 10, and the liquid crystal layer 11 is operated by an in-plane electric field L induced by the common electrode 17 and the pixel electrode 30.
FIGS. 2A and 2B are views illustrating operations in on and off states, respectively, of the IPS mode LCD.
Referring to FIG. 2A that shows arrangement of liquid crystal molecules in the on state, arrangement of the liquid crystal molecules 11a on the common and pixel electrodes 17 and 30 substantially remain unchanged as initial while arrangement of the liquid crystal molecules 110b between the common and pixel electrodes 17 and 30 is changed along the in-plane electric field L that is induced by applying voltages to the electrodes 17 and 30. In other words, since the liquid crystal molecules are operated by the in-plane electric field L, the IPS mode LCD can have wide viewing angles.
Accordingly, when the IPS mode LCD is viewed from the front, images is normally viewable up to about 80 degrees angle to about 85 degrees angle in up/down/left/right directions.
Referring to FIG. 2B that shows arrangement of liquid crystal molecules in the off state, since the in-plane electric field L is not induced between the common and pixel electrodes 17 and 30, arrangement of all liquid crystal molecules 11 substantially remains unchanged.
The IPS mode LCD has the advantage of wide viewing angles but has a disadvantage of low aperture ratio and transmittance.
To solve the problem of the IPS mode LCD device, a fringe field switching (FFS) mode LCD is suggested that is operated by a fringe field.
FIG. 3 is a cross-sectional view illustrating a FFS mode LCD according to the related art.
Referring to FIG. 3, on a substrate 31 of an array substrate of the FFS mode LCD, a light-blocking layer 33 is formed corresponding to a switching region TrA where a thin film transistor Tr is formed. A buffer layer 38 is formed on the light-blocking layer 33.
A semiconductor layer 50 made of polysilicon is formed in the switching region TrA on the buffer layer 38.
A gate insulating layer 55 is formed on the semiconductor layer 50, and a gate electrode 62 is in the switching region TrA on the gate insulating layer 55. An inter-layered insulating film 70 is formed on the gate insulating layer 70 and includes first and second semiconductor contact holes 73a and 73b. Source and drain electrodes 78 and 80 are formed on the inter-layered insulating film 70 and contacts the semiconductor layer 50 through the first and second semiconductor contact holes 73a and 73b, respectively.
The semiconductor layer 50, the gate insulating layer 55, the gate electrode 62, the inter-layered insulating film 70 and the source and drain electrodes 78 and 80 form the thin film transistor Tr.
A first passivation layer 85 is formed on the source and drain electrodes 78 and 80, and a common electrode 90 is formed on the first passivation layer 85 and includes a first opening op1 corresponding to the switching region TrA.
A second passivation layer 92 is formed on the common electrode 90. The first and second passivation layers 85 and 92 have a drain contact hole 93 exposing the drain electrode 80.
A pixel electrode 99 is formed in each pixel region P on the second passivation layer 92, contacts the drain electrode 80 through the drain contact hole 93, and includes a plurality of second openings op2 that each have a bar shape.
The array substrate of the FFS mode LCD is manufactured with 9 mask processes including a doping process for the semiconductor layer 50.
In other words, the array substrate is manufactured through a process of forming the light-blocking layer 33, a process of forming the polysilicon semiconductor layer 50, a process of forming a gate line (not shown) and the gate electrode 62, a process of forming the inter-layered insulating film 70 including the semiconductor contact holes 73a and 73b, a process of forming a data line (not shown) and the source and drain electrodes 78 and 80, a process of forming the first passivation layer 85, a process of forming the common electrode 90 including the first opening op1, a process of forming the second passivation layer 92, and a process of forming the pixel electrode 99 including the second openings op2.
Each mask process includes many unit processes, such as forming a material layer to be patterned on a substrate, forming a photoresist layer on the material layer, light-exposing the photoresist layer using a photo mask, developing the light-exposed photoresist layer, etching the material layer using a photoresist pattern that remains after the developing, and stripping the photoresist pattern.
To perform each mask process, a unit process apparatus and a material is needed for each unit process, and further, a time for each unit process is needed.
Accordingly, increase of the mask processes involves increase of production cost and time. Therefore, reduction of the mask processes is required to reduce production cost and time.